Because there is a continuing requirement to increase the integration density of integrated circuits, new techniques for creating a pattern on a surface such as a semiconductor wafer have been developed. One such technique is the electron beam lithography system and method in which electrons are directed onto the semiconductor surface to expose an electron sensitive resist coating on the surface. After exposure and development, the resist pattern is used as a template to effect patterned modifications on or to the underlying semiconductor substrate.
The classic electron beam lithography system is the "probe-forming" system in which a narrow beam that is the image of the electron source and having a Gaussian distribution is scanned over the surface to be exposed. The narrow beam is scanned a pixel at a time, the pixel being defined as the full width at half height of the beam intensity distribution. These systems can have the highest spatial resolution, but lowest throughput of all e-beam lithography systems due to the serial exposure of patterns one pixel at a time. The advantage of systems that serially expose patterns is that corrections can be applied dynamically pixel by pixel to compensate for aberrations of the electron lenses and deflection units in the system. Furthermore, if the pixel represents the smallest feature of the desired pattern, a pattern of any arbitrary complexity can be created with this type of probe. Proximity corrections are also easily made with this type of probe. An increase in throughput can be achieved by producing a larger spot on the wafer, adjustable in size and shape, so that it is equal to or greater than the minimum feature size of the circuit. Systems with this feature create a shaped spot on the wafer by generating an image of apertures or other objects illuminated by the source, that is, not an image of the source itself. The image is electronically variable in size and adjustable to compose a pattern feature with serial exposures projecting up to several hundred pixels in parallel. The images created are typically variable sized rectangles (including squares) or triangles.
More complicated shapes are created in cell block projection systems, see for example, H. C. Pfeiffer, IEEE Trans. Electr. Dev. ED26, 663(1979), where the image on the wafer is projected from a patterned mask at a conjugate image plane. Various patterns are available on the mask; they are selected by deflecting the illuminating beam to the appropriate pattern location on the mask. The patterns placed on the mask are those which are used repeatedly in a pattern on a chip on the semiconductor wafer so that each chip can be exposed with an economy of shots. This strategy is most efficient for circuits with a high degree of repetitiveness, such as DRAMs, and can lead to a significant increase in throughput.
Electron beam lithographic systems have been developed that utilize a particle beam source, a condenser lens system and a controllable aperture diaphragm having a line-shaped multi-hole structure for forming a plurality of particle beams, and a blanking diaphragm. Such devices are described in the following U.S. Pat. Nos. 4,724,328; 4,899,060; 4,982,099; and 4,996,441. U.S. Pat. No. 4,899,060 describes a diaphragm system forming a plurality of particle probes having a variable cross section. However, the particle probes described in the above patents are limited in number and are limited to linear arrays.
Throughput traditionally is measured by the number of wafers that can be patterned in an hour. An essential issue for all electron beam lithography systems is that throughput increases with increasing electron beam current delivered to the wafer; but the maximum current is limited by electron-electron and space charge considerations related to the basic repulsive Coulomb forces between electrons. These forces blur and distort the images on the wafer. This limit represents an important practical limit to throughput for existing electron beam lithography systems.
A charged beam lithography system having an improved throughput is described in Japanese Unexamined Patent Publication No. 60-31226, assigned to NTT (Nippon Telephone & Telegraph), having an application date of Aug. 1, 1983. This publication discloses a multi-beam device having the capability of blanking each beam independently by electrostatic deflection at the apertures that define each beam. The electrostatic deflection is controlled by electronic circuitry located adjacent to each aperture. A similar system is described in a Fujitsu Japanese Patent Publication No. 3-174715. Such architecture can allow a large number of beams. However, the circuitry is directly exposed to irradiation by electrons and x-rays, so its lifetime would be expected to be quite short. Furthermore, the beams in the NTT and Fujitsu devices are fixed sized beams that limit the capability of the device to create patterns of arbitrary size and shape. Only by using a system demagnification high enough that each beamlet is small enough to represent a pixel in the pattern would these systems be capable of creating arbitrary shapes. This would decrease the throughput of the system.
Other electron beam lithography systems are disclosed in Japanese Patent Publication Numbers: 05-166707; 07-263299; and 07-254540. These systems also create fixed shape multi-beams using independently blankable apertures. However, the aperture blanking is controlled by remote electronic circuitry. Each aperture blanker is independently connected to the remote electronics. The space required to route all of these connections limits the aperture array to be approximately one-dimensional. Thus, the total number of apertures is limited, as is throughput.
An electron beam projection system (EBPS) has been disclosed in U.S. Pat. No. 5,466,904 that uses a mask containing the entire chip pattern, however, only a small portion of the mask is illuminated with each exposure. Illuminating only a small portion of the mask relaxes the requirements for the electron optical system. The complete mask pattern is illuminated by a combination of the mechanical movement of the mask that is mounted on a movable reticle or mask stage and the deflection of the electron beam. The wafer stage is moved simultaneously with an appropriate deflection of the electron beam so that the illuminated area on the wafer chip site corresponds with the matching patterned area on the mask. Thus for each chip pattern, a new reticle must be constructed. As can be appreciated, the manufacture of the mask (reticle) for the EBPS is a challenging task and the required mechanical system is complicated, as two stages must move in exact synchronization to achieve a high degree of accuracy. In order to achieve a high throughput, high quality electron optics must be used that have a careful balance of optical aberrations to permit the use of high beam currents and also to permit high electron beam deflections.
The prior art can be summarized as follows. Relatively high throughput is possible with complicated systems employing reticles, which are expensive and difficult to build; a new reticle is needed for each new chip pattern to be produced. Greater flexibility and simplicity is obtained with systems which use a multiplicity of beamlets, which are created at an aperture plane and controlled by beam blanking deflectors associated with each beamlet. If the deflectors are controlled from electronics at a distance from the beam, the number of beamlets is limited by electrical connection problems. If deflection circuitry is located in proximity to each beamlet blanking deflector, the circuitry is rapidly destroyed by irradiation from electrons and x-rays. These beamlets are fixed in size, limiting their application. Further improvement in throughput in multi-beam systems would result from the inclusion of variable shape beamlets.
Accordingly, there is a need for a high-throughput electron beam lithography system that is capable of providing variable size and shape electron beamlets that can be individually blanked. In addition, there is a need for critical elements in the system to be shielded from the effects of radiation generated by the electrons or other charged particles striking surfaces within the lithography system.